This invention relates generally to memory and programmable logic devices having electrically programmable memory cells, and more specifically, to an improved two-transistor flash EPROM cell which prevents negative voltage thresholds after cell erasure and prevents conduction paths through the cell during programming subsequent to an erasure.
It is often desirable in digital systems to include memory which may be programmed in the field by the customer and later reprogrammed if necessary. It is also desirable to provide such programmable memory in a form where the information is stored in a nonvolatile manner, that is, in a manner where power is not required to maintain the stored information. Previously, fusible programmable logic devices were used to provide this on-site programmability. Because these devices relied on the physical destruction of fuses, however, reprogramming the memory device was impossible.
A family of devices, known as EPROMs, dependent upon avalanche charge injection or "hot" injection onto a floating-gate has evolved. In EPROMs, under the influence of a high applied drain voltage, charge collects on the floating gate where it is trapped by surrounding oxide insulation. The cell is erased by ultraviolet light which increases the energy of the floating gate electrons enabling them to jump the energy barrier and dissipate.
Another family of devices, known as EEPROMs or E.sup.2 PROMs can be electrically programmed and electrically erased. The basic technologies used to make E.sup.2 PROMs today typically rely on Fowler-Nordheim tunnelling, which is cold electron tunnelling through the energy barrier at a silicon-silicon dioxide interface. A thin oxide layer is required for this process. Flash EPROMs can be electrically programmed and electrically erased, yet typically allow a smaller memory cell size compared to the E.sup.2 PROM cell.
Programming flash EPROMs relies on charge injection. FIG. 1 is a schematic drawing of a small portion (4 cells) of a flash EPROM array such as in products sold by Intel Corporation. To program a flash EPROM cell 110, a high voltage is applied to the word line 112 to thereby raise the potential of gate 115. A high voltage is also applied to drain 114 of the cell to be programmed. This places a charge on the floating gate 118, adjusting the threshold voltage of the cell. Unlike the conventional EPROM cell which is erased by ultraviolet light, however, erasure of the cell 110 is dependent on Fowler-Nordheim tunneling. During erasure, the gate 115 of the flash EPROM cell is grounded, the source 116 is raised to a high voltage, and the drain 114 is allowed to float. These conditions allow charge on the floating gate to tunnel through the floating gate oxide and dissipate, leaving the floating gate unprogrammed.
Unfortunately, one of the problems associated with E.sup.2 PROM cells not found in conventional EPROM cells is the tendency for the voltage threshold of the device to become negative after erasure. This phenomenon does not occur in conventional EPROMs, where the floating gates return to the original voltage (zero volts) after erasure. In the flash EPROM cell, overerasure can leave the floating gate charged, resulting in a negative voltage threshold. A negative voltage threshold can prevent later accurate reading of the cell by the sense amplifier (coupled to drain 114). Typically when reading a particular cell 110 in a memory array, a logical "one" level is applied to the cell word line 112 for the row in which a cell is to be read and a logical zero level is applied to all other cell word lines, i.e., word lines not having the cell to be read. If the voltage threshold of the cell 110 which is to be read, however, is negative after the erasure, application of a low or zero voltage to the word line 112 will result in the overerased cell in word line 112 being turned on, which can prevent the sense amplifier from sensing a voltage differential. Thus, the sense amplifier may not be able to recognize the programming of which cell is on and may not be able to read a correct voltage.
Different flash EPROMs combat the problem of negative threshold voltage in a variety of ways. At the 1989 IEEE International Solid State Circuit Conference Session of Non-volatile Memory, a paper entitled "Nonvolatile Memories," by Kynett, et al., described a flash memory which controls the memory array erase threshold voltage by using an erase algorithm. Instead of using a single fixed pulse erase voltage, the described device changes the voltage pulse according to an erase algorithm to prevent overerasure.
A flash E.sup.2 PROM memory cell developed by Seeq Technology is shown in FIG. 2 and was described in the 1987 IEEE International Solid State Circuit Conference, Session VII of Non-volatile Memory. See "A 128K Flash EEPROM Using Double Polysilicon Technology," by Samachisa, et al. The flash E.sup.2 PROM transistor cell 210 is an integrated circuit structure which merges a floating gate transistor 212 in series with a NMOS transistor 214. If the erase voltage threshold of the floating gate transistor 212 becomes negative, the application of zero volts to the control gate of transistor 212 typically would turn on the transistor. Because of the NMOS transistor 214 in series with the floating gate transistor 212, however, the cell 210 has a voltage threshold of about +1 volt, and the cell 210 will not be turned on.
Although the Seeq flash E.sup.2 PROM solves the negative threshold voltage problem, there are problems associated with such a cell. Programming the Seeq flash E.sup.2 PROM device relies upon hot electron injection which is strongly dependent on the effective channel length. Dependency on the channel length is problematic because the channel in the Seeq transistor is not self-aligned, increasing the probability of punchthrough or longer programming times. Furthermore, the series NMOS transistor 214 adds to the cell resistance. This increased resistance makes hot electron programming more difficult, increasing the time needed to program the device.
Accordingly, a flash EPROM cell which decreases the time needed to program the cell, and which prevents a negative voltage threshold is needed.